There is a continuing need to increase the operating speed of digital systems. As is well known to those having skill in the art, a primary speed limiting factor is the integrated circuit logic and memory technology used in such systems. Several different technologies continue to be investigated in order to increase circuit speed. The basic technologies use bipolar transistors or field effect transistors (FET) or a combination thereof to form logic and memory circuits. In bipolar transistor technology, logic families such as emitter coupled logic (ECL) and transistor-transistor logic (TTL) have been designed. However, the basic drawback of bipolar transistor technology is the high power consumed by the circuits and the speed limitation of these circuits.
The art has also explored the use of FET based technologies. Most popular is the complementary metal oxide semiconductor (CMOS) technology in which complementary N-channel and P-channel FETs are used for logic and memory families. CMOS technology has great appeal because of the lack of DC power dissipation. In other words, logic and memory circuits only dissipate power when they are switching from one logic state to another but not when they are idling at a given logic state. CMOS circuits are also easy to manufacture using well developed silicon based technology. The basic drawback of CMOS, however, is its operating speed. Accordingly, the art has thoroughly investigated techniques for increasing the speed of CMOS circuits while still providing the basic advantages of CMOS. See for example U.S. Pat. No. 4,541,076 to Bowers et al. which discloses a technique for efficiently integrating a CMOS memory and CMOS logic gate array on a single substrate. See also the anonymous publication in Research Disclosure, September 1984, Number 245 entitled "High Speed CMOS NOR Circuit" which discloses a two-stage CMOS circuit for high speed logical operations.
Buffers have been used in logic and memory circuits in an attempt to enhance the operation thereof. See for example U.S. Pat. No. 4,802,132 to Ohsawa which discloses the use of buffers in a memory cell. U.S. Pat. No. 4,680,491 to Yokouchi et al. discloses a CMOS circuit having an output buffer for bidirectional input/output signals. U.S. Pat. No. 4,802,127 to Akaogi et al. discloses the use of plural inverters as an output buffer to reduce transient current multiplication by those output stages which would otherwise cause a significant rise in the potential level of the power source line in a semiconductor memory device.
The art has also investigated the use of inverters in logic and memory circuits to accomplish various purposes. See for example U.S. Pat. No. 4,209,713 to Satou et al. which discloses a CMOS inverter circuit. See also U.S. Pat. No. 4,825,420 to Min which discloses the use of buffer inverters to provide the correct signal polarity to control Schmitt triggers and memory addressing. See also U.S. Pat. No. 4,185,209 to Street which discloses the use of inverters to convert negative logic (NAND/NOR) CMOS technology into positive logic (AND/OR) technology.
The art has also investigated the use of bipolar and field effect transistors together in order to obtain the advantages of both. See for example U.S. Pat. No. 4,713,796 to Ogiue et al. which integrates bipolar and CMOS circuits for high speed operation. See also U.S. Pat. No. 4,740,718 to Matsui which integrates bipolar and CMOS circuits so that the CMOS logic controls the base current of a pullup NPN bipolar transistor. See also U.S. Pat. No. 4,808,850 to Masuda et al. which discloses inverters having unidirectional elements therein and Japanese published applications 55-45207 to Horie (published Mar. 29, 1980) and 60-141018 to Ozawa (published July 26, 1985) which disclose integrated bipolar and CMOS circuits which use diodes to connect the FETs and the bipolar transistors in order to suppress spike noise and provide high speed operation. A bipolar and CMOS logic gate which can function as either a CMOS or a bipolar logic circuit using the same devices and connections is shown in IBM Technical Disclosure Bulletin, Vol. 15, No. 8, January 1973, pp. 2571-2572 to Blose et al.
Notwithstanding the above described and other improvements, present state of the art CMOS circuits are limited to speeds of about 70 mHz. In an effort to provide higher speed logic and memory circuits, the art has also investigated exotic materials other than silicon, such as compound semiconductors like gallium arsenide and indium phosphide. However, these exotic materials often require discarding or reworking the large investment in silicon based processing equipment and techniques; require processing tolerances which are increasingly difficult to attain and also introduce their own set of problems for high speed operation.